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LTC4215/LTC4215-2
18
4215fe
 APPLICATIONS INFORMATION
For a start-up time of 4ms with a 2x safety margin we
choose:
 
C
t
ms 糉
C
C
ms
TIMER
STARTUP
SS
TIMER
=
+
=
2
12 3
10
8
"
.
/
"
112 3
7 5
10   0 68
.
/
.
"
.
ms 糉
nF
糉
+
E
Note the minimum value of C
TIMER
 is 10nF , and each 1nF
of soft-start capacitance needs 10nF of TIMER capaci-
tance/time during start-up.
The UV and OV resistor string values can be solved in the
following method. First pick R3 based on I
STRING
 being
1.235V/R3 at the edge of the OV rising threshold, where
I
STRING
 > 40糀. Then solve the following equations:
 
R2 =
V
V
" R3 "
UV
OV
OV(OFF)
UV(ON)
TH(RISING)
T
HH(FALLING)
UV(ON)
TH(RI
 R3
R1 =
V
UV
"(
)
R    R
3    2
+
SSING)
    
R    R
3    2
In our case we choose R3 to be 3.4k?to give a resistor
string current below 100糀. Then solving the equations
results in R2 = 1.16k?and R1 = 34.6k?
The FB divider is solved by picking R8 and solving for R7,
choosing 3.57k?for R8 we get:
 
R7 =
V
FB
PWRGD(UP)
TH(RISING)
"

R
R
8
8
resulting in R7 = 30k?
A 0.1糉 capacitor, C
F
, is placed on the UV pin to prevent
supply glitches from turning off the GATE via UV or OV .
The address is set with the help of Table 1, which indi-
cates binary address 1010011 corresponds to address
19. Address 19 is set by setting ADR2 high, ADR1 open
and ADR0 high.
Next the value of R5 and R6 are chosen to be the default
values 10?and 15k as discussed previously.
UV
OV
SS
GND
ON
EN
SDAO
FB
GPIO
INTV
CC
TIMER
ADIN
ADR2
ADR1
R2
R3
C
F
Z1
R1
SENSE RESISTOR R
S
C3
LTC4215UFD
R8
I
LOAD
4215 F05
I
LOAD
Figure 5. Recommended Layout
In addition a 0.1糉 ceramic bypass capacitor is placed on
the INTV
CC
 pin.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is required. The minimum trace width for 1oz copper
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530缉/?/SPAN>. Small resistances add up
quickly in high current applications. To improve noise
immunity, put the resistive dividers to the UV , OV and FB
pins close to the device and keep traces to V
DD
 and GND
short. It is also important to put the bypass capacitor for
the INTV
CC
 pin, C3, as close as possible between INTV
CC
 
and GND. A 0.1糉 capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply noise.
Figure 4 shows a layout that addresses these issues. Note
that a surge suppressor, Z1, is placed between supply and
ground using wide traces.
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